The present invention relates to a drive circuit for driving a group of driven elements such as, for example, an array of light emitting diodes (LEDs) disposed in an electro-photography printer as a light source, an array of heating resistors disposed in a thermal printer, and an array of display units disposed in a display device. The present invention also relates to a light emitting diode (LED) head including the drive circuit; and an image forming apparatus including the light emitting diode (LED) head.
In the specification, a light emitting diode may be referred to as an LED; a monolithic integrated circuit may be referred to as an IC; an n-channel MOS (Metal Oxide Semiconductor) transistor may be referred to as an NMOS transistor; and a p-channel MOS transistor may be referred to as a PMOS transistor.
Further, a high signal level may be referred to as a logical value of one (1), and a low signal level may be referred to as a logical value of zero (0), regardless of a positive logic or a negative logic. When it is necessary to differentiate the positive logic and the negative logic in a logical signal, “−P” may be added to an end of a positive logical signal, and “−N” may be added to an end of a negative logical signal.
In the following description, a group of driven elements is an array of LEDs used in an electro-photography printer as an example.
In a conventional image forming apparatus such as an electro-photography printer., a plurality of light emitting elements is arranged to form an exposure device. The light emitting element includes an organic EL and a light emitting thyristor, in addition to the light emitting diode (LED).
When the light emitting diode is used as a light source, a drive circuit is disposed to correspond to the light emitting element with each other, or to an N number of the light emitting elements (N>1). The light emitting element is switched between a turned-on state and a turned-off state when a current flows or stops flowing between an anode terminal and a cathode terminal thereof. When the LED emits light, a luminous output is determined by a drive current value. Accordingly, it is possible to adjust an exposure energy value of the exposure device through adjusting the drive current.
Patent Reference has disclosed a conventional drive circuit. In the conventional drive circuit, a first MOS transistor and a second MOS transistor constitute a series connection circuit. One of the first MOS transistor and the second MOS transistor operates in a saturated region all the time, thereby providing a constant current property for driving an LED with a constant current. Patent Reference: Japanese Patent Publication No. 09-291550 As described above, in the conventional LED drive circuit disclosed in Patent Reference, the first MOS transistor and the second MOS transistor constitute the series connection circuit. The first MOS transistor operates in the saturated region all the time, thereby providing the constant current property. The second MOS transistor is switching for controlling the drive of the LED. A control voltage is always supplied to a gate terminal of the first MOS transistor according to the drive current value to operate in the saturated region all the time, so that a drain terminal thereof is charged at a potential substantially the same as a power source potential.
Accordingly, when a drive on instruction signal is input to a gate terminal of the second MOS transistor, the second MOS transistor is turned on. As a result, the charged potential is discharged through the second MOS transistor and the LED without any control, thereby causing a sharp peak in a current waveform of the LED. The peak thus created has a current value depending on a small wiring resistivity inside the drive circuit, and the current value is significant enough to deteriorate the LED, thereby reducing a lifetime thereof.
The conventional drive circuit will be explained in more detail with reference to FIG. 19. FIG. 19 is a circuit diagram showing the conventional LED drive circuit. FIG. 19 shows a connection relationship of the LED drive circuit and a peripheral circuit thereof, and schematically represents one dot (for example, a surrounding area of the drive circuit of an LED element LED1).
As shown in FIG. 19, the conventional LED drive circuit includes a driver IC 81 represented with a hidden line; an LED array portion 82; a control voltage generation circuit 83 represented with a projected line; and a latch circuit 84 for one element. In the conventional LED drive circuit, the driver IC 81 has 192 of drive output terminals, so that there are provided 192 of the latch circuits 84, 192 of PMOS transistors 85 (described later), 192 of PMOS transistors 86 (described later), and the likes. On the other hand, the conventional LED drive circuit includes one control voltage generation circuit 83 per one driver IC 81.
In the conventional LED drive circuit, a source terminal of the PMOS transistor 85 is connected to a power source VDD, and a drain terminal thereof is connected to a source terminal of the PMOS transistor 86. A drain terminal of the PMOS transistor 86 is connected to a drive output terminal of a driver IC (not shown), and further connected to an anode terminal of the LED element LED1 of the LED array 82.
In the conventional LED drive circuit, an input terminal D of the latch circuit 84 is connected to an output terminal of a shift register (not shown), and an input terminal G thereof is connected to a latch signal HD-LOAD. An output terminal Q of the latch circuit 84 is connected to one of input terminals of an NAND gate 87, and an output terminal of the NAND gate 87 is connected to a gate terminal of the PMOS transistor 86. A strobe signal (not shown) is input into an input terminal of an inverter circuit 88, and an output terminal of the inverter circuit 88 is connected to the other of the input terminals of the NAND gate 87. A gate terminal of the PMOS transistor 85 is connected to an output terminal of an operational amplifier 89 (described later).
In the control voltage generation circuit 83, the operational amplifier 89 outputs an output voltage Vcon. The control voltage generation circuit 83 further includes a resistor 90 having a resistivity Rref and a PMOS transistor 91 having a gate length the same as that of the PMOS transistor 85. A reference voltage terminal VREF is connected to an inverse input terminal of the operational amplifier 89, and a reference voltage Vref is input to the reference voltage terminal VREF from a reference voltage circuit (not shown).
A source terminal of the PMOS transistor 91 is connected to the power source VDD, and a gate terminal thereof is connected to the output terminal of the operational amplifier 89. A drain terminal of the PMOS transistor 91 is connected to one end portion of the resistor 90 and a non-inverse input terminal of the operational amplifier 89. The other end portion of the resistor 90 is connected to ground.
The operational amplifier 89, the PMOS transistor 91, and the resistor 90 constitute a feedback control circuit. A current Iref flowing through the resistor 90, that is, the PMOS transistor 91, is not depended on the power source voltage VDD, and is determined only by the reference voltage Vref and the resistivity Rref of the resistor 90. Accordingly, the current Iref is given by:Iref=Vref/Rref
In the conventional LED drive circuit, a gate potential of the PMOS transistors 85 and 91 is equal to the voltage Vcont, and the PMOS transistors 85 and 91 have a same source potential. Accordingly, a voltage between the gate terminal and the source terminal of the PMOS transistor 85 is equal to that of the PMOS transistor 91, thereby having a current-mirror relationship. As a result, a current to be flowing in the PMOS transistor 85 is proportional to the current Iref flowing through the resistor 91. Accordingly, it is possible to adjust the drain current of the PMOS transistors 85 and 91 according to the reference voltage Vref, and to control a drive current of the LED element in the LED array 82 at a specific value.
In the conventional LED drive circuit, the PMOS transistor 86 is instructed to turn on according to print data latched with the latch circuit 84. At this time, a drain current generated in the PMOS transistor 86 is determined by a voltage between the gate terminals and the source terminals of the PMOS transistors 91 and 85. Accordingly, the PMOS transistor 86 functions as a switch element for switching the current.
An overshoot waveform of the drive current in the conventional LED drive circuit will be explained next. As shown in FIG. 19, a parasite capacitor 92 is created as a model of a floating capacitor inherently generated in the drain terminal of the PMOS transistor 85.
As described above, the reference voltage Vref is supplied to the control voltage generation circuit 83, and the reference current Iref determined by the reference voltage Vref flows in the PMOS transistor 91. The reference current Iref is dictated by the potential Vcont supplied to the gate terminal of the PMOS transistor 91. The voltage is applied to the gate terminal of the PMOS transistor 85 for tuning on the element.
When the PMOS transistor 86 is in an off state, the the floating capacitor 92 is charged up to a potential substantially the same as the power source voltage VDD. When the LED element LED1 is switched from on to off, the PMOS transistor 86 is switched from on to off. Accordingly, charges accumulated in the floating capacitor 92 are rapidly discharged to the LED element LED1, thereby causing a large overshoot in a waveform of the drive current at a rise portion thereof. When the charges are completely discharged, an anode current of the LED element LED1 has a value according to a drive state of the PMOS transistor 85, thereby leveling the large overshoot of the anode current of the LED element LED1.
FIG. 20 is a time chart showing an operation of the conventional LED drive circuit. In FIG. 20, print data are transferred with a HD-CLK signal and a HD-DATA signal. Then, transfer data are latched with a HD-LOAD signal, so that the LED element is driven with a strobe signal HD-STB-N according to the transferred data. When the strobe signal HD-STB-N rises at a point A, the LED element starts being driven, and a waveform of the drive current shows a large overshoot at a rise portion thereof.
As shown in FIG. 20, the drive current is leveled in a relatively short period of time, and is maintained at a specific value as indicated with a point B. When the strobe signal HD-STB-N becomes off, the drive current returns to zero as indicated with a point C. When the charges accumulated in the floating capacitor 92 shown in FIG. 19 are rapidly discharged toward the LED element through the switch formed of the PMOS transistor 86, the waveform of the drive current shows the large overshoot. The drive current is restricted with a resistor element such as an on resistivity of the PMOS transistor 86, a wiring resistivity inside the LED element, and the likes. The resistor element has a small resistivity, so that a level of the overshoot reaches a value a few tens of times of a designed drive condition of the LED element.
When such an excessive current flows in the LED element, even though it is for a short period of time, a large influence affects on the LED element, thereby deteriorating the LED element and changing a luminous efficiency thereof in a long run. As described above, the overshoot of the drive current is regulated with the resistor element such as the on resistivity of the PMOS transistor 86, the wiring resistivity inside the LED element, and the likes, and it is difficult to accurately control the resistor element. Accordingly, when an LED head includes a plurality of LED elements, each of the LED elements may have a different degree of deterioration after a long period of time, thereby causing a difference in a luminous efficiency thereof and causing an uneven print density.
Further, the conventional drive circuit has a noise voltage problem. More specifically, in the conventional drive circuit, the current waveform has a short rise time and a short fall time. When the drive current flowing in a large number of the LED elements is turned off concurrently in a short period of time, a large noise voltage tends to be generated.
More specifically, the noise voltage is given by:Voltage=L×ΔI/Δt where Δt is the rise time and the fall time of the current waveform, L is an inductance of a peripheral portion of the drive circuit, and ΔI is a change in the drive current.
When a printer is capable of printing on an A4 size sheet, an LED print head thereof has 4,992 of LEDs. Accordingly, even when the drive current for driving the LEDs is mere 1 mA, a peak current reaches about 5 A when all of the LEDs are turned on.
When the LED elements are turned off, the drive current is zero. When all of the LED elements are turned on, the drive current becomes 5 A, so that the change in the drive current ΔI becomes 5 A. When such a large current is switched in a short period of time, a large noise voltage is generated, thereby causing malfunction of the drive circuit or even damaging the drive circuit.
In view of the problems described above, an object of the present invention is to provide a drive circuit capable of solving the problems of the conventional drive circuit. In the drive circuit, it is possible to prevent an overshoot in a drive current upon driving an LED element, thereby preventing the LED element from deteriorating. A further object of the present invention is to provide an LED head and an image forming apparatus capable of preventing an uneven print density due to the overshoot. Further, an object of the present invention is to provide a drive circuit, and LED head, and an image forming apparatus capable of reducing a noise voltage.
Further objects and advantages of the invention will be apparent from the following description of the invention.